1. Field of the Invention
The invention relates to a memory cell having a vertical selection transistor, to an arrangement of such memory cells and to a method for producing these memory cells.
2. Description of the Related Art
Information can be stored and read out again with the aid of rewritable semiconductor memories. In the case of a DRAM semiconductor memory, the information is stored in the form of a particular charge in a storage capacitor. In this arrangement, each DRAM memory cell comprises one trench capacitor and one selection transistor. In the trench capacitor, a charge is stored which represents the information to be stored. The selection transistor, in contrast, is used as a switch for the writing and reading process. When the selection transistor of the memory cell is activated by means of the associated word line, the stored charge is transferred to a bit line of the semiconductor memory. The voltage of the bit line can be evaluated via an evaluation circuit so that the charge stored in the trench capacitor can be detected as information.
The performance of such memory cells is fundamentally determined both by the characteristics of the individual components themselves and by their interaction.
The continuous trend for memories with higher and higher capacity necessitates increasingly higher integration densities of the semiconductor patterns. To reduce the area required by DRAM memory cells, concepts with a vertically arranged selection transistor are also increasingly examined.
From DE 199 54 867 C1, a DRAM cell arrangement and a method for producing it is known in which a vertical selection transistor is provided. The known cell arrangement has a trench capacitor which is connected to a horizontally arranged source-drain region in the upper end area. A lower source-drain region which is connected to a vertical interconnection channel is formed offset with respect to the upper source-drain region. The interconnection channel is run from the lower source-drain region up to the bit line. In parallel with the interconnection channel, a gate region is formed which represents a part of a word line. The known cell arrangement has the disadvantage that a relatively large amount of area is needed for forming the memory cell.
From U.S. Pat. No. 6 262 448 B1, a generic memory cell, a corresponding arrangement of memory cells and a method for producing it are known.
From U.S. Pat. No. 5 561 308, a memory cell structure having an annular vertical TFT transistor is also known, the one electrode of which forms at the same time the inner capacitor electrode.